1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and particularly to a semiconductor memory circuit of a type wherein an on-chip decoder circuit and on-board circuits related to the decoder circuit have been improved.
2. Description of the Related Art
A decoder circuit employed in a semiconductor memory circuit has been disclosed in Japanese Laid-Open Patent Publication No. 60-138796, published on Jul. 23, 1985 of which the entire disclosure is incorporated herein by reference.
The disclosed semiconductor memory circuit is one of a type wherein decoder lines have been doubled for the purpose of achieving less power consumption and high-speed operations of decoder circuit. However, the disclosed decoder circuit needs many decoders. The patterns for the decoder circuit therefore require a larger lay out area when the decoder circuits are formed on a semiconductor chip. This is a clear disadvantage.